SystemVerilog code for arbitrary width random number utilities.
Needed an arbitrary width LFSR implementation. The one I've included works for 4 through 64 bits, but is easily extensible with the addition of more constants found using mlpolygen.
- Take files from
src/and add them to your own project. If you use hdlmake, you can add this repository itself as a remote module. - Other helpful modules are also available in this GitHub organization.
- Consult the testbench in
test/xorshift_tb.svfor example usage. - Read through the parameter descriptions in
xorshift.svand tailor any instantiations to your situation. - Please create an issue if you run into a problem or have any questions.
- Does not encompass all values (2 ** WIDTH-1 is missing)
- Predictable values, not suitable for any security-related application
See src/ring_oscillator.sv. Because the toggle rate of a ring oscillator depends on logic delays and noise, it can act as a source for truly random n-bit word data.
- This holds if and only if the sampling clock is lower than the natural oscillating frequency
- The quality of the produced random numbers is poor
- It can be improved by passing it through an LHCA, in which case, it will pass all the DieHard tests
See src/lhca.sv. LFSR generalization suitable for cryptographic applications when sourced with a ring oscillator.
- Xorshift (LFSR)
- Ring oscillators
- LHCA backed by Ring Oscillators
- CBRNG
- Making the Squares RNG arbitrary width seems non-trivial, unfortunately
- More upon request
These documents are not hosted here!
- High Speed True Random Number Generators in Xilinx FPGAs
- This is the primary source for the LHCA concept