hillhao
2016-2017, University of Birmingham, Embedded System, MSc 2006-2008, Tianjin University, Microelectronics, MS 2002-2006, Tianjin University, EE, BS
ZEALYNC Beijing R&D CenterBeijing, China
Pinned Repositories
chisel3
Chisel 3: A Modern Hardware Design Language
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
firrtl
Flexible Intermediate Representation for RTL
Neural-Network-and-NLP
neual network,nlp,python, tensorflow,nltk,theano
PYNQ-project
PYNQ, Neural network Language model, Overlay
ReinforceingLearning
RL theory and practices
riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
rocket-chip
Rocket Chip Generator
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
zscale
Z-scale Microarchitectural Implementation of RV32 ISA
hillhao's Repositories
hillhao/PYNQ-project
PYNQ, Neural network Language model, Overlay
hillhao/Neural-Network-and-NLP
neual network,nlp,python, tensorflow,nltk,theano
hillhao/ReinforceingLearning
RL theory and practices
hillhao/chisel3
Chisel 3: A Modern Hardware Design Language
hillhao/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
hillhao/firrtl
Flexible Intermediate Representation for RTL
hillhao/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
hillhao/rocket-chip
Rocket Chip Generator
hillhao/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
hillhao/zscale
Z-scale Microarchitectural Implementation of RV32 ISA