/Project-1

This repo is for my Project 1 class.

Primary LanguageVerilogThe UnlicenseUnlicense

PROJECT-1

This repo is for my Project 1 class.

My task is to implement AES-256 algorithm on FPGA.

FOLDER STRUCTURE

  • Diagrams: contains diagrams, flowcharts
  • Docs: contains LaTeX source for the paper about AES
  • Refs: contains reference papers, documents
  • src: contains Verilog source code and other scripts