huangxc6

Peking UniversityBeijing

Pinned Repositories

Digital_IC_Design_23fall
Here are some assignments for digital integrated circuit design in the fall of 2023.Welcome to communicate and star.
Language:Verilog2 1 00
E203_CNN_Genesys2
Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
Language:VHDL10 1 00
Embedded_Microprocessor_System_24Spring
2024 Spring Semester Embedded Microprocessor System Assignment School of Software and Microelectronics, Peking University.
Language:Assembly21
huangxc6
Config files for my GitHub profile.
0 1 00
MIT_6.175_6.375_Lab
MIT 6.004 6.175 6.375 course, notes, Lab and Project. digital design and computer architecture.
Language:C10
Software_Hardware_Co-Design_24Spring
Hardware and software collaborative design labs and project in the spring semester of 2024
Language:Verilog2 1 00
SPI_MS
Final Project - Fa23 (a “SPI_MS Chip” that allows full-duplex, synchronous, serial communication between the Chip and peripherals.)
Language:SystemVerilog4 1 00
tutorial
Some software installation and usage tutorials
00
verilog_oj
Reference designs for some oj topics
Language:Verilog00
verilog_practice
Verilog implementation of some simple modules
Language:Verilog00

huangxc6/E203_CNN_Genesys2
Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
Language:VHDL10 1 00
huangxc6/SPI_MS
Final Project - Fa23 (a “SPI_MS Chip” that allows full-duplex, synchronous, serial communication between the Chip and peripherals.)
Language:SystemVerilog4 1 00
huangxc6/Digital_IC_Design_23fall
Here are some assignments for digital integrated circuit design in the fall of 2023.Welcome to communicate and star.
Language:Verilog2 1 00
huangxc6/Embedded_Microprocessor_System_24Spring
2024 Spring Semester Embedded Microprocessor System Assignment School of Software and Microelectronics, Peking University.
Language:Assembly21
huangxc6/Software_Hardware_Co-Design_24Spring
Hardware and software collaborative design labs and project in the spring semester of 2024
Language:Verilog2 1 00
huangxc6/MIT_6.175_6.375_Lab
MIT 6.004 6.175 6.375 course, notes, Lab and Project. digital design and computer architecture.
Language:C10
huangxc6/huangxc6
Config files for my GitHub profile.
0 1 00
huangxc6/tutorial
Some software installation and usage tutorials
00
huangxc6/verilog_oj
Reference designs for some oj topics
Language:Verilog00
huangxc6/verilog_practice
Verilog implementation of some simple modules
Language:Verilog00