1, Quick Start

1.1, Download and install miniconda

https://docs.conda.io/en/latest/miniconda.html

1.2, Create Python environment

Open anaconda prompt from win start -> Anaconda3 -> Anaconda Prompt

It is recommended to install PyAEDT in a clean virtual environment.

$ conda create -n pyaedt_env python=3.10 # Python version can be specified when create virtual environment
$ activate pyaedt_env

Install PyAEDT and relevant packages

$ pip install pyaedt
$ pip install networkx

How to update PyAEDT to the latest version.

$ pip install -U pyaedt

1.3, How to run python script in spyder

Click here

2, Introduction

This project is built on top of PyAEDT. DCIR_Automation is licenced under the MIT License.

This script demonstrates an automated workflow to extract and visualize power tree. The input file can be either EDB or tel netlist. There are two classes

1, class PowerTreeSchematic takes tel netlist as input.

2, class PowerTree takes EDB as input.

2.1, PowerTreeTel exmaple

from dcir_power_tree.netlist_process import PowerTreeTel
from dcir_power_tree import PowerRail

# Define test point refdes naming convention
PowerTreeTel.TP_PRIFIX = ["TP", "INC"]
# Define fuse refdes naming convention. All fuses will be replaced by a resistor
PowerTreeTel.REPLACE_BY_RES = ["F"]
# Define connector refdes naming convention
PowerTreeTel.CONNECTOR_PRIFIX = ["X", "J"]
# Define ground net name
PowerTreeTel.GROUND = ["GND"]
# Exclude components by refdes explicitly
PowerTreeTel.COMP_EXCLUDE_LIST = []
# Exclude component pin explicitly
PowerTreeTel.COMP_PIN_EXCLUDE_LIST = ["U2A5.E1"]

# Whether to exlucde connector from power tree
PowerTreeTel.EXCLUDE_CONNECTOR = True

# Example on Galileo board

targetfile = r"example\galileo.tel"
print(targetfile)
PowerTreeTel(
    fpath=targetfile,
    bom="galileo_exmaple/bom_galileo.csv",
    power_rail_list=[
        PowerRail(
            prim_refdes_pin="U3A1.37", voltage=1.0,
            sec_refdes_pin_list=[],
            sink_power_info="example/U3A1-BST_V1P0_S0.csv"),

        PowerRail(prim_refdes_pin="U3A1.14", voltage=3.3),
    ],
    nexxim_sch=True
)

Power tree is saved in temp folder as png files. The power tree is generated by networkx algorithm. If the placement is not optimal, just re-run the script.

Extracted sinks are saved in csv file in temp folder.

The same power tree is created in Nexxim for DC analysis.