Pinned Repositories
back_translate
Data augmentation with Back Translation
free-programming-books
:books: Freely available programming books
machine-learning-coursera
it's stored by exercises(pdf, my code by Octave/MATLAB)in course Machine Learning Andrew Ng
meetup
Meetup info
OpenTimer
SystemVerilogReference
training labs and examples
tacotron2
An implementation of Tacotron and Tacotron2
UDEMY_AXI_InfrastructureBasedonXilinx
Udemy Lectures Materials
verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
hungnguyen08's Repositories
hungnguyen08/back_translate
Data augmentation with Back Translation
hungnguyen08/free-programming-books
:books: Freely available programming books
hungnguyen08/machine-learning-coursera
it's stored by exercises(pdf, my code by Octave/MATLAB)in course Machine Learning Andrew Ng
hungnguyen08/meetup
Meetup info
hungnguyen08/OpenTimer
hungnguyen08/SystemVerilogReference
training labs and examples
hungnguyen08/tacotron2
An implementation of Tacotron and Tacotron2
hungnguyen08/UDEMY_AXI_InfrastructureBasedonXilinx
Udemy Lectures Materials
hungnguyen08/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
hungnguyen08/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.