huwenao's Stars
CandyConfident/HighPerformanceConcurrentServer
基于C++11、部分C++14/17特性的一个高性能并发httpserver,包括日志、线程池、内存池、定时器、网络io、http、数据库连接等模块。模块间低耦合高内聚,可作为整体也可单独提供服务。对各模块提供单元测试,对httpserver整体提供性能测试。
hansionz/ConcurrentMemoryPool
📚一个三级缓存的高并发内存池
Winter-Win/ConcurrentMemoryPool
youcaiguai/NetServer
A C++ High Performance NetServer
guoxuanhan/NetServer
本项目为C++11编写的基于epoll的多线程网络服务器框架,应用层实现了简单的http服务器和一个回声服务器,其中http解析和get方法请求,目前支持静态资源访问,支持http长连接;
happyfish100/fastdfs
FastDFS is an open source high performance distributed file system (DFS). It's major functions include: file storing, file syncing and file accessing, and design for high capacity and load balance. Wechat/Weixin public account (Chinese Language): fastdfs
linyacool/WebServer
A C++ High Performance Web Server
xiaodainiao/fastdfs
基于c++实现的分布式文件传输系统
CMU-SAFARI/ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
sumonbis/PathORAM
Path ORAM is a simple oblivious RAM algorithm. While using cloud platform or any other insecure memory, attack can be made using the access pattern. Oblivious RAM is the way to hide the memory access pattern with some extra bandwidth and memory overhead.
thanghoang/S3ORAM
Implementation of S3ORAM (CCS'17 & ACM TOPS'20)
hiroki-chen/Oblivious-RAM
A reference implementation of some ORAM algorithms.
NVlabs/timeloop
Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.
stonne-simulator/stonne
STONNE: A Simulation Tool for Neural Networks Engines
Fraunhofer-AISEC/DATA
Differential Address Trace Analysis
nvdla/hw
RTL, Cmodel, and testbench for NVDLA
CMU-SAFARI/ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Xilinx/CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
nvdla/firesim-nvdla
FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
dhm2013724/yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
airockchip/librga
AFLplusplus/AFLplusplus
The fuzzer afl++ is afl with community patches, qemu 5.1 upgrade, collision-free coverage, enhanced laf-intel & redqueen, AFLfast++ power schedules, MOpt mutators, unicorn_mode, and a lot more!
rockchip-linux/rknpu2
airockchip/rknn_model_zoo
orangepi-xunlong/orangepi-build
Orange Pi build for H2+, H3, H5, H6, H616, RK3328, RK3399 and RK3588(s)
orangepi-xunlong/linux-orangepi
Joshua-Riek/ubuntu-rockchip
Ubuntu for Rockchip RK35XX Devices
airockchip/rknn-toolkit2
scalesim-project/scale-sim-v2
Repository to host and maintain scale-sim-v2 code
pwndbg/pwndbg
Exploit Development and Reverse Engineering with GDB Made Easy