/colab

计算机组成原理实验。

Primary LanguageVerilog

Pipeline CPU in ISE

CPU Core is implemented with self-written verilog files, while others are provided by the tutor. Because configurations are not listed(and I'm even so lazy that I won't fix it), it's nearly impossible to clone the entire repo and build the project. But I'm sure the verilog files do work.

42 kinds of MIPS instructions are supported. Details can be found in def.v file.