According to VexiiRiscv Doc, install dependencies. At lease make sure sbt and verilator can run in your machine.
then clone submodules using:
git submodule update
Run benchmark:
make coremarksee makefile:
| make cmd | optimization |
|---|---|
| coremark0 | increase L1 cache ways to 4 |
| coremark1 | increase L1 cache size to 8KB |
| coremark2 | add store buffer slot 4 |
| coremark3 | add ras brach prediction |
| coremark4 | decrease memory latency to 4 |
| coremarkl2 | add 32KB L2 Cache |