hyperpicc

hyperpicc's Stars

• westerndigitalcorporation/swerv-ISS

  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

  20041

• lajanugen/Modular-Exponentiation

  Verilog Implementation of modular exponentiation using Montgomery multiplication

  Language:Verilog307

• raya4213/VerilogCodeECC

  Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field

  Language:Jupyter Notebook2011

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.7k488

• lecram/gifenc

  small C GIF encoder

  Language:C25634

• ridecore/ridecore

  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

  Language:Verilog30361

• jeras/sockit_spi

  SocKit SPI (3-wire, dual, quad) master

  Language:Verilog51

• jeras/sockit_owm

  SocKit 1-wire (onewire) master

  Language:C186

• risclite/R8051

  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

  Language:Verilog15441

• jaruiz/light52

  Yet another free 8051 FPGA core

  Language:VHDL288

• borancar/Embedded-8051-based-Cryptosystem

  An embedded 8051-based crypto system with a cryptographic coprocessor

  Language:VHDL32

• freecores/light52

  Lightweight 8051 compatible CPU

  Language:VHDL42

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.1k652

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog899397

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k995

• secworks/trng

  True Random Number Generator core implemented in Verilog.

  Language:Verilog7115

• secworks/aes

  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

  Language:Verilog318119

• secworks/sha512

  Verilog implementation of the SHA-512 hash function.

  Language:Verilog3321

• secworks/sha256

  Hardware implementation of the SHA-256 cryptographic hash function

  Language:Verilog30589

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog2.9k715

• VerticalResearchGroup/miaow

  An open source GPU based off of the AMD Southern Islands ISA.

  Language:Verilog996234

• RoaLogic/adv_jtag_bridge

  Language:C35

• RoaLogic/adv_dbg_if

  Universal Advanced JTAG Debug Interface

  Language:SystemVerilog1611

• RoaLogic/universal_jtag_tap

  Universal JTAG TAP Controller

  Language:SystemVerilog95

• RoaLogic/ahb3lite_interconnect

  AHB3-Lite Interconnect

  Language:SystemVerilog8026

• RoaLogic/ahb3lite_apb_bridge

  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

  Language:SystemVerilog3919

• RoaLogic/plic

  Platform Level Interrupt Controller

  Language:SystemVerilog3413

• RoaLogic/RV12

  RISC-V CPU Core

  Language:SystemVerilog27550

• RoaLogic/ahb3lite_memory

  Multi-Technology RAM with AHB3Lite interface

  Language:SystemVerilog1916

• asicguy/gplgpu

  GPL v3 2D/3D graphics engine in verilog

  Language:VHDL644142