Pinned Repositories
ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
chip_architect
Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
chisel-minicpu
keras2cpp_env
llvm
Mirror of official llvm git repository located at http://llvm.org/git/llvm. Updated every five minutes.
riscv-isa-manual
RISC-V Instruction Set Manual
vagrant-env
Vagrant files for building experimental environments
i4kimura's Repositories
i4kimura/chisel-minicpu
i4kimura/chip_architect
Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
i4kimura/ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
i4kimura/keras2cpp_env
i4kimura/llvm
Mirror of official llvm git repository located at http://llvm.org/git/llvm. Updated every five minutes.
i4kimura/riscv-isa-manual
RISC-V Instruction Set Manual
i4kimura/vagrant-env
Vagrant files for building experimental environments
i4kimura/A64FX
i4kimura/aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
i4kimura/docker-env
Environment for building Docker
i4kimura/firechip
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
i4kimura/firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud (e.g. RISC-V Rocket Chip, BOOM, and more)
i4kimura/fpga-zynq
Support for Rocket Chip on Zynq FPGAs
i4kimura/fpga_ips
IP repository for FPGA implementation
i4kimura/freedom-e-sdk
Open Source Software for Developing on the Freedom E Platform
i4kimura/freedom-u-sdk
Freedom Unleashed Software Development Kit
i4kimura/github_pages
GitHub Pages
i4kimura/hdl
HDL libraries and projects
i4kimura/hw
RTL, Cmodel, and testbench for NVDLA
i4kimura/keras2cpp
This is a bunch of code to port Keras neural network model into pure C++.
i4kimura/libfixmath
Cross Platform Fixed Point Maths Library
i4kimura/micropython
MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems
i4kimura/riscv-compliance
i4kimura/riscv-cq-interface
Interface RISC-V Running
i4kimura/riscv-isa-sim
Spike, a RISC-V ISA Simulator
i4kimura/riscv-pk
RISC-V Proxy Kernel
i4kimura/riscv-tools
RISC-V Building Environment Chef recipes
i4kimura/rocket-chip
Rocket Chip Generator
i4kimura/swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores