Pinned Repositories
MGP-2022-HW
Smart-Infinity
[HPCA'24] Smart-Infinity: Fast Large Language Model Training using Near-Storage Processing on a Real System
bwa
Burrow-Wheeler Aligner for short-read alignment (see minimap2 for long-read alignment)
CLRDRAM
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf
endasim
fast-interconnects
Research project on scaling GPU-accelerated data management to large data volumes. Code base of two SIGMOD papers.
FPGA_ECE8893
iamjinholee.github.io
SIGPLAN.github.io
SIGPLAN website
SIGPLAN.github.io
SIGPLAN website
iamjinholee's Repositories
iamjinholee/bwa
Burrow-Wheeler Aligner for short-read alignment (see minimap2 for long-read alignment)
iamjinholee/CLRDRAM
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf
iamjinholee/endasim
iamjinholee/fast-interconnects
Research project on scaling GPU-accelerated data management to large data volumes. Code base of two SIGMOD papers.
iamjinholee/FPGA_ECE8893
iamjinholee/iamjinholee.github.io
iamjinholee/SIGPLAN.github.io
SIGPLAN website