iammituraj
RTL Design Engineer, Technical Blogger, Philanthropist, Teacher ....
Chipmunk Logic™India
Pinned Repositories
apb
APB master and slave developed in RTL.
debouncer
Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.
FIFOs
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
gcd_calculator
GCD calculator with APB Slave interface.
iammituraj
Bio
LIFO-Stack
Register-based LIFO aka Stack designed in Verilog/System Verilog.
pequeno_riscv
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
pqr5asm
PQR5ASM is a RISC-V Assembler compliant with RV32I
reset_and_cdc_synchronizers
Reset and CDC synchronizers developed in Verilog/System Verilog.
skid_buffer
Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
iammituraj's Repositories
iammituraj/pequeno_riscv
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
iammituraj/FIFOs
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
iammituraj/skid_buffer
Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
iammituraj/pqr5asm
PQR5ASM is a RISC-V Assembler compliant with RV32I
iammituraj/apb
APB master and slave developed in RTL.
iammituraj/debouncer
Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.
iammituraj/LIFO-Stack
Register-based LIFO aka Stack designed in Verilog/System Verilog.
iammituraj/reset_and_cdc_synchronizers
Reset and CDC synchronizers developed in Verilog/System Verilog.
iammituraj/gcd_calculator
GCD calculator with APB Slave interface.
iammituraj/iammituraj
Bio
iammituraj/style-guides
lowRISC Style Guides
iammituraj/tweak_circuits
Tweak circuits designed in VHDL/Verilog like CDC synchronizers: Pulse synchronizer, Reset synchronizer, Two-flop synchronizer, Edge detectors, Pulse generators, Clock gating etc.
iammituraj/vsd_hdp_chipcron
Database related to VSD-HDP workshop in association with Chipcron