Pinned Repositories
aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
apb
APB Logic
ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
biriscv
32-bit Superscalar RISC-V CPU
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
cmsdk_ahb_busmatrix
practice configure AHB-Lite bus protocol
common_cells
Common SV components
libuvc-for-vs2017
Xilinx-Unprotect
iceshy's Repositories
iceshy/Xilinx-Unprotect
iceshy/apb
APB Logic
iceshy/ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
iceshy/axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
iceshy/biriscv
32-bit Superscalar RISC-V CPU
iceshy/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
iceshy/common_cells
Common SV components
iceshy/core_spiflash
SPI-Flash XIP Interface (Verilog)
iceshy/cores
Various HDL (Verilog) IP Cores
iceshy/Cores-SweRV
SweRV EH1 core
iceshy/edalize
An abstraction library for interfacing EDA tools
iceshy/FRV2100
PulseRain FRV2100 RISC-V Core
iceshy/hackdac_2018_beta
The SoC used for the beta phase of Hack@DAC 2018.
iceshy/ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
iceshy/iob-soc
RISC-V System on Chip Template
iceshy/openocd
Spen's Official OpenOCD Read-Only Mirror (no pull requests)
iceshy/opentitan
OpenTitan: Open source silicon root of trust
iceshy/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
iceshy/PulseRain_RISCV_MCU
PulseRain RISC-V MCU
iceshy/PulseRain_rtl_lib
PulseRain rtl library
iceshy/ReGDS-Logic-Gate-Extraction
A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
iceshy/riscv
RISC-V CPU Core (RV32IM)
iceshy/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
iceshy/rocket-chip
Rocket Chip Generator
iceshy/senior_design_puf
Repository to store all design and testbench files for Senior Design
iceshy/serv
SERV - The SErial RISC-V CPU
iceshy/sha256
Hardware implementation of the SHA-256 cryptographic hash function
iceshy/TimEx
Netlist-to-Verilog extraction for SFQ circuits
iceshy/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
iceshy/yosys
Yosys Open SYnthesis Suite