Penn Implementation of Computation Group
Research Group in Electrical and Systems Engineering and Computer and Information Science Departments at University of Pennsylvania
Philadelphia, PA
Pinned Repositories
bert
Bitstream Embedded RAM Transfusion
ese532_code
ese532_handouts
Course handouts for ESE532 at UPenn
estream4fccm2021
hipr
nestedDFX
This is repo to show how to use nested DFX on ZCU102 board
pld2022
prflow_nested_dfx
Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
prflow_REFINE
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs (FPGA 2024)
rosetta_vitis
Penn Implementation of Computation Group's Repositories
icgrp/hipr
icgrp/pld2022
icgrp/prflow_nested_dfx
Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
icgrp/bert
Bitstream Embedded RAM Transfusion
icgrp/ese532_code
icgrp/prflow_REFINE
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs (FPGA 2024)
icgrp/rosetta_vitis
icgrp/ese532_handouts
Course handouts for ESE532 at UPenn
icgrp/asym_bft
Asymmetry in Butterfly Fat Tree FPGA NoC (FPT 2023)
icgrp/doblink
icgrp/estream4fccm2021
icgrp/nestedDFX
This is repo to show how to use nested DFX on ZCU102 board
icgrp/symbiflow-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
icgrp/adaptive_timing_repair
icgrp/edalize
An abstraction library for interfacing EDA tools
icgrp/fpga-tool-perf
FPGA tool performance profiling
icgrp/huffmanVivadoProject
huffmanVivadoProject submodule for bert
icgrp/hydra
Hydra is a framework for elegantly configuring complex applications
icgrp/old_systolic_placer
Updated systolic placer
icgrp/prjxray
Documenting the Xilinx 7-series bit-stream format.
icgrp/pythondata-cpu-vexriscv-stream
Python module containing verilog files for vexriscv cpu (for use with LiteX).
icgrp/rosetta
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
icgrp/slurm-gcp
Slurm on Google Cloud Platform
icgrp/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research