ijor/fx68k

Issues

• SystemVerilog to Verilog conversion seems to be successful

  #16 opened 6 months ago by Willyarma
  3

• Is BGACKn behavior correct?

  #15 opened a year ago by tcdev42
  4

• Warnings by GoWin IDE

  #14 opened a year ago by harbaum
  2

• Zolt

  #13 opened 2 years ago by Antonkalmyk
  1

• Not compatible with iVerilog

  #2 opened 2 years ago by jotego
  18

• Usage of synthesis on / off

  #12 opened 2 years ago by udif
  6

• Enumerated value used on its own in if condition

  #11 opened 3 years ago by jotego
  2

• X assignments

  #10 opened 3 years ago by jotego
  2

• Hidden bug

  #7 opened 4 years ago by jotego
  15

• subq instruction bug

  #9 opened 4 years ago by jotego
  2

• How to request the bus?

  #4 opened 4 years ago by jotego
  6

• HALT input signal.

  #1 opened 5 years ago by srg320
  4

• Possible issue with UNLK

  #3 opened 5 years ago by apolkosnik
  2