ilesser

Pinned Repositories

caravel_user_project
https://caravel-user-project.readthedocs.io
Language:Verilog0 0 00
cocotb
Coroutine Co-simulation Test Bench
Language:Python0 1 00
dotfiles
My dotfiles
Language:Vim Script0 1 00
familytreemaker
Generates a family tree graph from a simple text file
Language:Python0 1 00
litex
Build your hardware, easily!
Language:C0 0 00
litex-boards
LiteX boards files
Language:Python0 0 00
nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
Language:C++0 0 00
OpenDB
Database and Tool Framework for EDA
Language:C++0 0 00
OpenRCX
Language:C++0 0 00
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
Language:Verilog0 0 00

ilesser's Repositories

ilesser/caravel_user_project
https://caravel-user-project.readthedocs.io
Language:Verilog0 0 00
ilesser/cocotb
Coroutine Co-simulation Test Bench
Language:Python0 1 00
ilesser/dotfiles
My dotfiles
Language:Vim Script0 1 00
ilesser/familytreemaker
Generates a family tree graph from a simple text file
Language:Python0 1 00
ilesser/litex
Build your hardware, easily!
Language:C0 0 00
ilesser/litex-boards
LiteX boards files
Language:Python0 0 00
ilesser/nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
Language:C++0 0 00
ilesser/OpenDB
Database and Tool Framework for EDA
Language:C++0 0 00
ilesser/OpenRCX
Language:C++0 0 00
ilesser/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
Language:Verilog0 0 00
ilesser/OpenROAD-flow
OpenROAD's top level repo pointing to stable binaries, code, sample designs and an example flow
Language:Verilog0 0
ilesser/OpenSTA
OpenSTA engine
Language:C++0 0
ilesser/RapidWright
Build Customized FPGA Implementations for Vivado
Language:Java0 0
ilesser/TritonMacroPlace
Macro placement tool for OpenROAD flow
Language:C++0 0
ilesser/xfire
Language:TeX1 22