Implemented a FIFO Shift Register in Verilog, with parametrized width and depth, as well as a testbench.
The descriptions of the files included are as follows:
• Implementation Summary.pdf - A summary of the design and the implementation reports
• FIFO_shift_reg_beh.v - The Verilog description of the FIFO Shift Register
• FIFO_shift_reg_beh_tb.v - Test bench for testing the device
• constraints.xdc - Timing constraints for the synthesis
• Simulation Results.wcfg - Waveforms generated after the simulation
This is the beginning of my journey with Verilog, and hence I haven't touched on the finer aspects of the design such as timing, area, and power consumption. Please tweak the design according to your requirements, and avoid using it as it is (as it might not be optimal for your purposes).