/FPGA

Primary LanguageVHDL

FPGA

#board: ZYNQ XC7Z020-CLG484-1

#IDE: Vivado 2018.3

FPGA練習進度

PPT_website:

counter,PWM: https://docs.google.com/presentation/d/12_NmClu6HN7DbbVjxDnpB8zjuy3ViTyR/edit?usp=share_link&ouid=103027492385642734663&rtpof=true&sd=true

VGA_pong: https://docs.google.com/presentation/d/1p63Hg1SRnq0yNkkL3FAKqPgmDp7prSw4/edit?usp=sharing&ouid=103027492385642734663&rtpof=true&sd=true

VGA_clock: https://docs.google.com/presentation/d/1EzO3roLt0gmvVqBIuCxsLtbWYxsPmWKJ/edit?usp=sharing&ouid=103027492385642734663&rtpof=true&sd=true

VGA_pong_BRam: https://docs.google.com/presentation/d/1jL8wnBCBdbjSs01VLU42yXEWj280P2HN/edit?usp=sharing&ouid=103027492385642734663&rtpof=true&sd=true