DRP addresses in drp_decl are too narrow
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The DRP address width is defined as nine bits:
https://github.com/ipbus/ipbus-firmware/blob/master/components/ipbus_slaves/firmware/hdl/drp_decl.vhd#L41
However, there are many DRP ports around that are wider. For example the GTY common DRP addresses are ten bits (see table 2-24 in https://www.xilinx.com/support/documentation/ip_documentation/gtwizard_ultrascale/v1_1/pg182-gtwizard-ultrascale.pdf). Under certain conditions these addresses are actually generated with a 16-bit width, but that may be a Vivado issue.
Could we please just bump this address width definition to 16 bits everywhere, and trust the optimiser to get rid of any unused bits?
Ok, after a bit of digging, and reading the latest version of the documentation (https://www.xilinx.com/support/documentation/ip_documentation/gtwizard_ultrascale/v1_7/pg182-gtwizard-ultrascale.pdf, table 2-24), it turns out that the UltraScale+ GTH and GTY indeed have 16-bit COMMON DRP addresses.
I'll generate a pull request preparing for an expansion of the DRP address in drp_decl.vhd.