Bug in constraints file for Enclustra AX3
Opened this issue · 1 comments
The constraints file for the Enclustra AX3 has two buggy lines
File: boards/enclustra_ax3_pm3/synth/firmware/ucf/enclustra_ax3_pm3.tcl
offending lines are
false_path {phy_rstn} osc_clk
false_path {leds[*]} osc_clk
These two line give warnings when building with Vivado 2019.2 . ( Was this ever valid syntax?? )
Suggest replacement with something like:
set_false_path -through [get_ports phy_rstn]
set_false_path -through [get_ports leds[*]]
Relevant for DUNE timing system and AIDA-2020 TLU which both use the AX3
diff --git a/boards/enclustra_ax3_pm3/synth/firmware/ucf/enclustra_ax3_pm3.tcl b/boards/enclustra_ax3_pm3/synth/firmware/ucf/enclustra_ax3_pm3.tcl
index e46c619..0e4ef90 100644
--- a/boards/enclustra_ax3_pm3/synth/firmware/ucf/enclustra_ax3_pm3.tcl
+++ b/boards/enclustra_ax3_pm3/synth/firmware/ucf/enclustra_ax3_pm3.tcl
@@ -49,8 +49,7 @@ set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
-false_path {phy_rstn} osc_clk
+set_false_path -through [get_ports phy_rstn]
LED pin constraints
set_property IOSTANDARD LVCMOS25 [get_ports {leds[]}]
@@ -59,7 +58,7 @@ set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
set_property PACKAGE_PIN L18 [get_ports {leds[2]}]
set_property PACKAGE_PIN M18 [get_ports {leds[3]}]
-false_path {leds[]} osc_clk
+set_false_path -through [get_ports leds[*]]