Add test coverage for ipbus ram slaves

[alessandrothea]

The existing automatic tests don't provide appropriate coverage of the ipbus ram slave code.
Dedicated tests have to be added, covering

• VHDL Syntax
• Interface with ipbus
• interface with the payload clock logic

The latter will require adding a dedicated pattern generator.

[alessandrothea]

Note: Both dpram36 and spdpram72 were found to be inferred as distributed RAMs while expected to be implemented as block rams. The code has been slightly re-arranged according to the Xilinx prescriptions. They are both inferred as block RAMs, now.