This started out as a simple demonstration of what was possible with the video interfaces on a Zybo FPGA, but has since evolved into the backbone of my Masters Thesis.
This repository contains IP cores meant to be used in Vivado. The VHDL source files are surely usable in other tools, but I do not actively provide support for that workflow.
The general_ip folder contains IP blocks that are not directly for video processing. This folder contains useful utility blocks.
The video_ip folder contains IP blocks for video processing. Most of these are designed as VGA stream blocks. That is, they take in an clocked pixel input and produce some transformed output.
The examples folder contains full top-level Vivado projects that can be run through Synthesis, Layout and Bitstream generation and then programmed onto the Zybo. They demonstrate the utility of the IP cores included in this repository.
You must use Vivado 2016.4 or later.
On Windows, you may want to clone this repo closer to the root of your drive. I use C:\ZyboIP. Windows has issues with long paths, and Vivado will exhibit unusual behavior if the paths exceed the character limit.