j2kevin18

j2kevin18's Stars

• codecrafters-io/build-your-own-x

  Master programming by recreating your favorite technologies from scratch.

  Language:Markdown361k5.9k74333.5k

• torvalds/linux

  Linux kernel source tree

  Language:C190k7.8k055.3k

• deepseek-ai/DeepSeek-V3

  Language:Python92.7k72446615.1k

• deepseek-ai/DeepSeek-R1

  87k61848611.2k

• rswier/c4

  C in four functions

  Language:C10k328331.5k

• mit-pdos/xv6-riscv

  Xv6 for RISC-V

  Language:C7.7k921132.9k

• albertan017/LLM4Decompile

  Reverse Engineering: Decompiling Binary Code with Large Language Models

  Language:Python5.3k5843365

• hneemann/Digital

  A digital logic designer and circuit simulator.

  Language:Java4.7k93956480

• stellarkey/912_project

  清华大学计算机系考研攻略 Guidance for postgraduate entrance examination in Department of Computer Science and Technology, Tsinghua University

  Language:HTML2.7k719529

• etched-ai/open-oasis

  Inference script for Oasis 500M

  Language:Python1.8k2440147

• InternLM/Tutorial

  LLM&VLM Tutorial

  Language:Python1.7k20831.6k

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.4k3721360

• liangkangnan/tinyriscv

  A very simple and easy to understand RISC-V core.

  Language:C1.2k168201

• LoveLonelyTime/Bergamot

  An exquisite superscalar RV32GC processor.

  Language:Scala1513313

• peilin-chen/Zhulong-RISCV-CPU

  CPU Design Based on RISCV ISA

  Language:Verilog954020

• OSCPU/ysyxSoC

  Language:Verilog796336

• xiaowuzxc/SparrowRV

  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.

  Language:Verilog604017

• OSCPU/yosys-sta

  Language:Verilog5941114

• renyangang/riscv-mcu

  This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral circuit simulation. The goal is to support system boot, startup, operation, interrupt handling, peripheral control, and other functions.

  Language:Verilog492111

• zhuozhiyongde/PKU-Auto-Reservation

  北京大学/北大/PKU自动预约入校

  Language:Python44114

• Azalea8/riscv_cpu

  riscv指令集，单周期以及五级流水线CPU

  Language:Verilog43101

• USTC-System-Courses/CECS-Lab

  Language:C340012

• luzhixing12345/archlab

  NUDT 高级体系结构实验

  Language:Python33116

• Jin-bao/NCU-thesis

  南昌大学学位（毕业）论文 LaTeX 模板

  Language:TeX30252

• KevinVan720/xv6-gui

  xv6 OS

  Language:C29100

• MengYueqi/HIT_CPU_verilog

  哈工大2023处理器设计与计算机体系结构实验

  Language:Verilog182

• FlyMachinee/project-pipeline

  Language:Verilog10101

• Paraoia/CS-Cache

  Design a cache by using Verilog

  Language:Verilog7100

• wind2412/wind_os

  my simple os kernel

  Language:C6212

• xforcevesa/RobustCore

  RobustCore: A Robust CPU Core Fully Built On Chisel HDL

  Language:Scala6100