Pinned Repositories
basic_verilog
Must-have verilog systemverilog modules
cocotbext-axi
AXI interface modules for Cocotb
cocotbext-eth
Ethernet interface modules for Cocotb
cocotbext-pcie
PCI express simulation framework for Cocotb
dotfiles
用于记录vim/emacs的用户配置文件
ethernet-switch
Ethernet switch implementation written in Verilog
hexo
A fast, simple & powerful blog framework, powered by Node.js.
Ocean
pyuvm
The UVM written in Python
SpinalHDL
Scala based HDL
jackey-2020's Repositories
jackey-2020/basic_verilog
Must-have verilog systemverilog modules
jackey-2020/cocotbext-axi
AXI interface modules for Cocotb
jackey-2020/cocotbext-eth
Ethernet interface modules for Cocotb
jackey-2020/cocotbext-pcie
PCI express simulation framework for Cocotb
jackey-2020/dotfiles
用于记录vim/emacs的用户配置文件
jackey-2020/ethernet-switch
Ethernet switch implementation written in Verilog
jackey-2020/hexo
A fast, simple & powerful blog framework, powered by Node.js.
jackey-2020/Ocean
jackey-2020/pyuvm
The UVM written in Python
jackey-2020/SpinalHDL
Scala based HDL
jackey-2020/tools
Config files for my GitHub profile.
jackey-2020/uvm-systemc
jackey-2020/verilator
Verilator open-source SystemVerilog simulator and lint system
jackey-2020/verilog-axi
Verilog AXI components for FPGA implementation
jackey-2020/verilog-ethernet
Verilog Ethernet components for FPGA implementation
jackey-2020/verilog-pcie
Verilog PCI express components