jackzhang1992

jackzhang1992's Stars

• feifei14119/KmtHsaStudy

  Language:C1

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k668

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.2k670

• pulp-platform/pulp

  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

  Language:SystemVerilog436114

• iDalink/ld-linker-script

  GNU ld linker script 介绍 博客 链接脚本

  Language:C14945

• VerticalResearchGroup/miaow

  An open source GPU based off of the AMD Southern Islands ISA.

  Language:Verilog1k235

• vherdt/riscv-vp

  RISC-V Virtual Prototype

  Language:C++3561

• google/googletest

  GoogleTest - Google Testing and Mocking Framework

  Language:C++34.2k10k

• ZipCPU/zipcpu

  A small, light weight, RISC CPU soft core

  Language:Verilog1.3k153

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog920409

• riscv-non-isa/riscv-arch-test

  Language:Assembly499188

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3k745

• micro-FPGA/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog2

• open-design/riscv-soc-cores

  Language:Verilog3710

• qmn/riscv-invicta

  A simple RISC-V core, described with Verilog

  Language:Verilog2510

• SpinalHDL/VexRiscvSoftcoreContest2018

  Language:Verilog6316

• rsnikhil/RISCV_Piccolo_v1

  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

  Language:Verilog335

• ultraembedded/riscv

  RISC-V CPU Core (RV32IM)

  Language:Verilog1.2k223

• ataradov/riscv

  Verilog implementation of a RISC-V core

  Language:Verilog10119

• diningyo/fpga-scr1

  fpga simulation and synthesis for scr1 which designed by syntacore

  1

• syntacore/scr1-sdk

  open-source SDKs for the SCR1 core

  Language:C6631

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog835267

• RoaLogic/RV12

  RISC-V CPU Core

  Language:SystemVerilog28050

• micro-FPGA/riscv-contest-2018

  RISCV SoftCPU Contest 2018

  144

• cnrv/home

  为推广RISC-V尽些薄力

  Language:SCSS30459

• zephyrproject-rtos/zephyr

  Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

  Language:C10.4k6.4k

• riscv-software-src/riscv-tools

  RISC-V Tools (ISA Simulator and Tests)

  Language:Shell1.1k446

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k1k

• RISCV-on-Microsemi-FPGA/Hardware-Platforms

  Hardware-Platforms

  75

• RISCV-on-Microsemi-FPGA/Documentation

  Documentation relevant to the available repositories on RISCV-on-Microsemi-FPGA

  139