learn_HDL
This is my repo for all code related to the HDL-course in sys. verilog at FHV. It contains examples and excercises from the courses and weekly assignments. Goal is to create an own MCU (as FPGA) which is able to compute Tetris.
This is my repo for all code related to the HDL-course in sys. verilog at FHV. It contains examples and excercises from the courses and weekly assignments. Goal is to create an own MCU (as FPGA) which is able to compute Tetris.