The RCA 1802 in Verilog.
If you have Verilator installed then you should be able to build the simulator, and even run CamelForth 1802 interactively:
$ make
...
$ obj_dir/Vtestbench software/CF1802.hex
RCA1802 CamelForth v1.3 18 Oct 2014
1 2 + .
3
ok WORDS
.SYMBOL TRACE ROLL CS-ROLL PICK CS-PICK 2R@ 2R> 2>R RESTORE-INPUT
SAVE-INPUT [THEN] [IF] [ELSE] REFILL SOURCE-ID ENDCASE ENDOF OF CASE
AHEAD BEGINLOOP ?DO 0> 0<> UNUSED MARKER FORGET (FORGET) CONVERT
CREATE1 [COMPILE] 1. 2CONSTANT 2VARIABLE TO FINDWORD VALUE :NONAME
? DUMP .ADDR .BYTE .R U.R S.RJ ERASE BLANK SEARCH COMPARE -TRAILING \
SLITERAL CCSTR C" (C") .( PARSE COLD .S WORDS ENVIRONMENT? DEPTH MOVE
WITHIN LEAVE +LOOP LOOP ENDLOOP DO L> >L REPEAT WHILE AGAIN UNTIL
BEGIN ELSE THEN IF COMPILE POSTPONE ['] ; : IMMEDIATE REVEAL HIDE ]
[ RECURSE DOES> (DOES>) CREATE (CREATE) ( [CHAR] CHAR ' ABORT"
?ABORT ABORT QUIT EVALUATE INTERPRET DICTERR ?NUMBER >NUMBER ?SIGN
DIGIT? LITERAL FIND (FIND) NFA>CFA NFA>LFA WORD >COUNTED /STRING
SOURCE C, , ALLOT HERE HEX DECIMAL . U. SIGN #> #S # >DIGIT <# HOLD
UD* UD/MOD ." S" (S") TYPE ACCEPT UMAX UMIN SPACES SPACE CR COUNT
2OVER 2SWAP 2DUP 2DROP 2! 2@ MIN MAX */ */MOD MOD / /MOD * FM/MOD
SM/REM M* DABS ?DNEGATE DNEGATE ABS ?NEGATE S>D #INIT UINIT R0 L0
PAD S0 LP HP LATEST 'SOURCE DP STATE BASE >IN U0 TIB #TIB TIBSIZE
BL !DEST ,DEST ,BRANCH ,EXIT COMPILE, >BODY CHARS CHAR+ CELLS CELL+
CELL ALIGNED ALIGN S= SCAN SKIP CMOVE> CMOVE FILL UM/MOD UM* UNLOOP J
I (+loop) (loop) (do) ?BRANCH BRANCH U> U< > < <> = 0< 1 TRUE FALSE
0 -1 0= +! RSHIFT LSHIFT 2/ 2* >< 1- 1+ NEGATE INVERT XOR OR AND -
M+ + C@ @ C! ! RP! RP@ SP! SP@ R@ R> >R TUCK NIP ROT OVER SWAP DROP
DUP ?DUP BYE KEY EMIT ALIAS USER CONSTANT VARIABLE EXECUTE EXIT
ok