复旦大学2018-2019学年春季学期
Spring 2020, Fudan University
Computer Architecture Lab 计算机体系结构实验 (COMP130013.01)
This is our semester-long lab for our Computer Architecture course. In this project, we are asked to implement a MIPS CPU with System Verilog.
Our lab is divided into three stages: Single Cycle MIPS CPU, Pipelined MIPS CPU, Pipelined MIPS CPU with cache. You can access my code for each stage in the "Release" page and my reports in the "report" folder.