A 4-stage pipeline, Harvard architecture, Thumb CPU implemented on an Altera DE1 FPGA.
- Program Counter (PC) is updated with current branch value.
- Instruction Memory (ROM) reads PC value and outputs new opcode.
- Interprets ROM Opcode.
- Determines which registers must be read from.
- Stalls pipeline if necessary.
- Performs operation based on opcode.
- Flags may be set.
- Data Memory (RAM) may be written to.
- If no Stall, will return to Fetch stage.
- RAM performs write into Register File.
- Returns to Fetch stage.
A Stall will occur if a Load (LDR) opcode is read. This is necessary to guarantee the registers are loaded with the correct memory before the next instruction performed.
IN PROGRESS
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Harvard Architecture.
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Implements ARM Thumb (16-bit) instruction set.
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1024, 16-bit, ROM locations.
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512, 32-bit, RAM locations.
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The pipeline currently meets all timing constraints under a 50 MHz clock. More work will be done to increase this number.
- Finish instruction set implementation.
- Mitigate Stalls by recording necessary data from Load instruction, and feed to requesting instruction.