jayeshsuyal

Pinned Repositories

Verification-of-APB_RAM
Language:SystemVerilog20
3to8_decoder
Implementation of a 3 to 8 Decoder using Verilog
Language:Verilog00
APB_RAM_AXI3
Language:SystemVerilog01
jayeshsuyal
Config files for my GitHub profile.
00
UART
Language:SystemVerilog00
Verification-of-I2C-
Language:SystemVerilog00
whishbone-memory
Language:SystemVerilog00

jayeshsuyal's Repositories

jayeshsuyal/Verification-of-APB_RAM
Language:SystemVerilog2
jayeshsuyal/Verification-of-I2C-
Language:SystemVerilog
jayeshsuyal/APB_RAM_AXI3
Language:SystemVerilog1
jayeshsuyal/UART
Language:SystemVerilog
jayeshsuyal/whishbone-memory
Language:SystemVerilog
jayeshsuyal/3to8_decoder
Implementation of a 3 to 8 Decoder using Verilog
Language:Verilog
jayeshsuyal/jayeshsuyal
Config files for my GitHub profile.