A Static Compiler translating from Synthesizable Verilog-like source-code to Logisim circle .
- main : main branch
- branch_semantic : frontend,Maintained by DorMouse
- backend : backend,Maintained by HaoHao
python >=3.6
spark-parser package :
1、download package from Link
2、install package
python setup.py install # may need sudo
# or if you have pyenv:
python setup.py develop
Editing with Typora ,generate PDF automatically .
Details in VeriSim/设计文档.pdf