I roughly followed this video but did it in zig.
Maybe using async proper "cycles" could be done (e.g. every time cycles is decremented, suspend). need to wait for zig to implement async in stage 2 tho (or go back to 10.1 but i probably wont)
- add extra tests for every opcode to cover every possible case
- Consider whether cpu should have mem as a field and internally access it.
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Consider analyzing the bits of the opcodes to see if it makes sense to separate the instruction from the addressing mode and generate the opcode on the fly.- Ended up just using the enum names & comptime to generate switch statements for both instruction & addressing mode.
I may or may not finish this. IDK how "clean"/"cool" this code is, so pls don't judge me too hard.