jeonghyunwoo0306
Ph.D. student in ECE at the University of British Columbia.
The University of British ColumbiaVancouver, BC Canada
Pinned Repositories
lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
ece408PJ_Fa2020
gem5-nvmain-hybrid-simulator
gem5-nvmain hybrid simulator supporting simulation of DRAM-NVM hybrid memory system
homepage_updated
jeonghyunwoo0306.github.io
lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
Pythia
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
scale-srs
scale-srs
jeonghyunwoo0306's Repositories
jeonghyunwoo0306/ece408PJ_Fa2020
jeonghyunwoo0306/gem5-nvmain-hybrid-simulator
gem5-nvmain hybrid simulator supporting simulation of DRAM-NVM hybrid memory system
jeonghyunwoo0306/homepage_updated
jeonghyunwoo0306/jeonghyunwoo0306.github.io
jeonghyunwoo0306/lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
jeonghyunwoo0306/Pythia
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
jeonghyunwoo0306/ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
jeonghyunwoo0306/scale-srs