jeremiah-c-leary/vhdl-style-guide

Missing one space in alignment of aggregate parts

Closed this issue · 3 comments

maltaisn commented

The following file:

library ieee;
  use ieee.std_logic_1164.all;

entity b is
end entity b;

architecture a of b is

  signal s : MY_TYPE := (
                          a => '0',
                          ddddd => (others => '0'),
                          ffff => (others => '0')
                        );

begin

end architecture a;

With the configuration:

rule:
  signal_007:
    disable: yes

Produces:

library ieee;
  use ieee.std_logic_1164.all;

entity b is
end entity b;

architecture a of b is

  signal s : MY_TYPE := (
                          a => '0',
                         ddddd => (others => '0'),
                          ffff => (others => '0')
                        );

begin

end architecture a;

Notice the misalignment of ddddd by one space.

JHertz5 commented

Hi @maltaisn. I've identified the source of this problem and put together a PR (#1308) to correct the issue. If you get a chance, please try out the branch and let me know whether you agree that it solves the problem.

maltaisn commented

It works, thanks for the fix.

  • ❤️1
jeremiah-c-leary commented

Afternoon @JHertz5 and @maltaisn ,

PR looks good, I will get this merged to master.

Thanks,

--Jeremy

  • ❤️1