jerralph
Computer Engineering. 20+ years of experience in Chip Design/Verification, Software and Firmware Development.
bigco Vancouver Island
Pinned Repositories
riscv-vip
For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
riscv-vip-scr1-demo
Demo of riscv-vip integration with the Syntacore SCR1 RISC-V core
scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog. This fork illustrates how the riscv-vip can be added to the testbench.
jerralph's Repositories
jerralph/riscv-vip
For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
jerralph/riscv-vip-scr1-demo
Demo of riscv-vip integration with the Syntacore SCR1 RISC-V core
jerralph/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog. This fork illustrates how the riscv-vip can be added to the testbench.