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jgyllinsky/RISC-V-TensorCore
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
VerilogMIT
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
VerilogMIT
This repository is not active