jimmysitu

CPU Micro Architect

ZHAOXIN, JMST1KHujLT4AzQwQKSLEUSbcergqv7fMnQNXA

Pinned Repositories

bitcoind-openwrt-packages
Build bitcoind full node on openwrt, so you can run your full bitcoin node on your router
Language:Makefile4 3 17
espresso2verilog
Simplify logic and translate to verilog
Language:C4 2 01
FormalCourseExercise
Exercise of Formal Verification Courseware
Language:Verilog3 1 00
gem5-bench
A wrapper for simulation with gem5
Language:Python4 1 05
msfinance
msfinance offers Pythonic way to download market data from morningstar.com
Language:Python10 1 12
oss-cvc
CVCx is a fork of OSS CVC from Tachyon DA
Language:C5 1 11
verilog-axi-formal
Formal verification for alexforencich/verilog-axi using SymbiYosys
Language:Verilog6 2 01
verilog-sim-benchmarks
Verilog Simulator Benchmarks, a fork from verilator website
Language:C6 1 00
vtags
Verdi like, verilog code signal trace and show hierarchy script
Language:Python19 2 22

jimmysitu's Repositories

jimmysitu/msfinance
msfinance offers Pythonic way to download market data from morningstar.com
Language:Python10 1 12
jimmysitu/verilog-axi-formal
Formal verification for alexforencich/verilog-axi using SymbiYosys
Language:Verilog6 2 01
jimmysitu/gem5-bench
A wrapper for simulation with gem5
Language:Python4 1 05
jimmysitu/FormalCourseExercise
Exercise of Formal Verification Courseware
Language:Verilog3 1 00
jimmysitu/verilog2smt
Example to transform verilog to smtlib2
Language:Verilog1 2 0
jimmysitu/jmRocket
Jimmy's Rocket Chip
Language:Python0 1 00
jimmysitu/api-v1-client-python
Blockchain Bitcoin Developer APIs - Python
Language:Python1 01
jimmysitu/ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
Language:SystemVerilog1 0
jimmysitu/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Language:Assembly1 0
jimmysitu/gem5
Jimmy's gem5, forked from
Language:C++1 01
jimmysitu/GeST
GeST (Generating Stress-Tests) is a Genetic Algorithm framework for automatic hardware stress-test generation. Related scientific publication https://ieeexplore.ieee.org/document/8695639
Language:Python1 0
jimmysitu/jimmysitu
Config files for my GitHub profile.
1 0
jimmysitu/jimmysitu.github.io
JM's website on github
Language:Ruby2 0
jimmysitu/jmACL2
JM's ACL2 playground
Language:Common Lisp2 0
jimmysitu/jmBenchmark
Jimmy's Benchmark
Language:Shell1 0
jimmysitu/jmCool
Jimmy's Cool Compiler, for https://lagunita.stanford.edu/courses/Engineering/Compilers/Fall2014/info
Language:Java1 0
jimmysitu/jmRocket-SDK
SDK for jmRocket
Language:C1 0
jimmysitu/jmStockAnalysis
Jimmy's stock analysis
Language:Python1 0
jimmysitu/likwid
Performance monitoring and benchmarking suite
Language:C1 0
jimmysitu/More_Equal_Animals_Chinese_Edition
《更平等的动物》中文版
Language:JavaScript1 0
jimmysitu/nZDC-Compiler
A LLVM-3.7 compiler with nZDC error detection transfromation
Language:C++0 0
jimmysitu/oh
Silicon proven Verilog library for IC and FPGA designers
Language:Verilog1 0
jimmysitu/pyParallelTest
Just a python3 parallel example
Language:Python2 0
jimmysitu/silifuzz
JM's silifuzz
Language:C++
jimmysitu/spring23
Problem Sets for MIT 6.512 Formal Reasoning About Programs, Spring 2023
Language:Coq0 0
jimmysitu/stx_cookbook
Altera Advanced Synthesis Cookbook 11.0
Language:Verilog1 0
jimmysitu/veriformal
This repository contains source code of VeriFormal simulator and translator.
1 0
jimmysitu/verilog-axi
Verilog AXI components for FPGA implementation
Language:Verilog1 0
jimmysitu/vhdlformal
This repository stores the source code of a domain-specific language: a formalized version of VHDL embedded in Isabelle/HOL.
Language:Isabelle1 0
jimmysitu/waveform-render-vscode
Render waveforms inside VSCode with WaveDrom
Language:TypeScript1 0