Pinned Repositories
behavioral-model
The reference P4 software switch
chisel-template
A template project for beginning new Chisel work
chisel3
Chisel 3: A Modern Hardware Design Language
chocolatey-packages
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
deeplearning_ai_books
deeplearning.ai（吴恩达老师的深度学习课程笔记及资源）
e200_opensource
The Ultra-Low Power RISC Core
ethmac
Ethernet MAC 10/100 Mbps
ethmac10g
10G Ethernet MAC
ieee_gptp
you can generate 802.1as gptp pcap
jiru000000's Repositories
jiru000000/ieee_gptp
you can generate 802.1as gptp pcap
jiru000000/behavioral-model
The reference P4 software switch
jiru000000/chisel-template
A template project for beginning new Chisel work
jiru000000/chisel3
Chisel 3: A Modern Hardware Design Language
jiru000000/chocolatey-packages
jiru000000/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
jiru000000/deeplearning_ai_books
deeplearning.ai（吴恩达老师的深度学习课程笔记及资源）
jiru000000/e200_opensource
The Ultra-Low Power RISC Core
jiru000000/ethmac
Ethernet MAC 10/100 Mbps
jiru000000/ethmac10g
10G Ethernet MAC
jiru000000/gen_amba
AMBA bus generator including AXI, AHB, and APB
jiru000000/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
jiru000000/knitkit
jiru000000/knitkit-doc
Knitkit Document
jiru000000/myhdl
The MyHDL development repository
jiru000000/nfmac10g
Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
jiru000000/p4benchmark
you can use this project to generate pcap used as transceiver
jiru000000/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
jiru000000/PYNQ
Python Productivity for ZYNQ
jiru000000/reed_solomon_decoder
Reed Solomon Decoder (204,188)
jiru000000/STM32F7-IEEE1588-2008-implementation
jiru000000/verilog-ethernet
Verilog Ethernet components for FPGA implementation
jiru000000/vim-script
jiru000000/wujian100_open
IC design and development should be faster，simpler and more reliable