Counter Detection design and test bench
Create RTL that does the following:
// Detect if the input series of data is incrementing or decrementing
// Input to the DUT are clk, reset & 4 bit data input
// Output from the DUT are incr, decr, error
// If data increases by 1, flag the incr output as 1
// If data decreases by 1, flag the decr output as 1 else flag the error output as 1