jix/nerv

Naive Educational RISC V processor

NERV - Naive Educational RISC-V Processor

NERV is a very simple single-stage RV32I processor. It is equipped with an RVFI interface and is formally verified.

Running the simulation testbench

git clone https://github.com/yosyshq/nerv.git
cd nerv
make

Running the riscv-formal testbench

git clone https://github.com/yosyshq/riscv-formal.git
cd riscv-formal/cores/
git clone https://github.com/yosyshq/nerv.git
cd nerv
make -j8 check

iCEBreaker SOC example

See the iCEBreaker SOC README