jmcgreen

jmcgreen's Stars

• PyHDI/veriloggen

  Veriloggen: A Mixed-Paradigm Hardware Construction Framework

  Language:Python30458

• hnikolov/pihdf_doc

  The source of the pyhdf documentation

  Language:HTML1

• hnikolov/pihdf

  Python Hardware Design Framework based on MyHDL

  Language:Python2

• nkavaldj/myhdl_lib

  A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.

  Language:Python163

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k668

• wavedrom/wavedrom.github.io

  Digital timing diagram editor

  Language:JavaScript918159