Pinned Repositories
CADApps
VLSI CAD Algorithm Visualizations implemented as Java Applications
Conways-Game-Of-Life
delete.me2
test, check if we can push etc
ece414-examples
RP2040 Sample Code for ECE 414 at Lafayette College
flowreg-dally
Register with ready-valid flow control based on Dally & Harting Example 22.1
hw_pq
A family of hardware priority queue implementations
MazeRouterApp
Visualization of VLSI Maze Routing Algorithms (Lee, Hadlock, A*)
PlacementApp
Animation of VLSI Placement/Floorplanning using Simulated Annealing or Iterative Improvement
SV_Examples
SystemVerilog examples - common building blocks
systolic_pq
A SystemVerilog implementation of Lieserson's Systolic Priority Queue
jnestor's Repositories
jnestor/CADApps
VLSI CAD Algorithm Visualizations implemented as Java Applications
jnestor/SV_Examples
SystemVerilog examples - common building blocks
jnestor/PlacementApp
Animation of VLSI Placement/Floorplanning using Simulated Annealing or Iterative Improvement
jnestor/hw_pq
A family of hardware priority queue implementations
jnestor/systolic_pq
A SystemVerilog implementation of Lieserson's Systolic Priority Queue
jnestor/ece414-examples
RP2040 Sample Code for ECE 414 at Lafayette College
jnestor/MazeRouterApp
Visualization of VLSI Maze Routing Algorithms (Lee, Hadlock, A*)
jnestor/Conways-Game-Of-Life
jnestor/delete.me2
test, check if we can push etc
jnestor/flowreg-dally
Register with ready-valid flow control based on Dally & Harting Example 22.1
jnestor/L4_PCI_32x32
L4 Maze Routing Accelerator
jnestor/led_matrix_controller
FPGA Hardware to control the AdaFruit 16x32 LED Matrix.
jnestor/life_core
Hardware Core for Conway's Game of Life
jnestor/mips_L_multi
This is a modified version of the Single-Cycle MIPS processor design from Digital Design and Computer Architecture" (2nd ed.) by David M. Harris and Sarah L. Harris (Morgan-Kaufmann, 2013).
jnestor/mips_L_pipeline
jnestor/mips_L_single
Extended MIPS single-cycle pedagogical design from Harris & Harris "Digital Design and Computer Architecture"
jnestor/NewChannelRouter
jnestor/otieno_research
Summer Design Projects with Maurice Otieno
jnestor/sr_pq
Shift Register Hardware Priority Queue
jnestor/SteinerApp
Visualization of rectilinear Steiner and Minimum Spanning Trees
jnestor/sw_pq
Various software implmeentations of priority queues, including a Java implementation of the heap-based priority queue described in Ch. 5 of Cormen, Leiseson, Rivest & Stein
jnestor/TSP_Simulator
Tiled Spatial Processing Simulator
jnestor/valid_ready
SystemVerilog implementation of Valid-Ready Interface