joaocarlos/udlx-verilog

Issues

• Pin/Port Definitions updating for Memory stage

  #13 opened 11 years ago by igoamauri
  0

• Internal datapath and Pin/Port Definitions updating for Execute stage

  #10 opened 11 years ago by igoamauri
  0

• Internal datapath and Pin/Port Definitions updating for Write back stage

  #11 opened 11 years ago by igoamauri
  0

• Internal datapath planning for Memory

  #5 opened 11 years ago by joaocarlos
  0

• Internal datapath and Pin/Port Definitions updating for Instruction Fetch stage

  #9 opened 11 years ago by igoamauri
  0

• Describe Execute block and Pin/Port definicionts

  #1 opened 11 years ago by joaocarlos
  3

• Control Unit signal planning

  #8 opened 11 years ago by joaocarlos
  0

• Update Pipeline Register Description

  #12 opened 11 years ago by igoamauri
  0

• Internal datapath planning for Execute stage

  #4 opened 11 years ago by joaocarlos
  2

• Internal datapath planning for Instruction Decode stage

  #3 opened 11 years ago by joaocarlos
  0

• Internal datapath planning for Write Back stage

  #6 opened 11 years ago by joaocarlos
  0

• Plan datapath pipeline registers function

  #7 opened 11 years ago by joaocarlos
  0

• Internal datapath planning for Instruction Fetch stage

  #2 opened 11 years ago by joaocarlos
  0