joestoy

Pinned Repositories

• ssith-aws-fpga

  Host software for running SSITH processors on AWS F1 FPGAs

  Language:Verilog17644

• AHB-Lite

  AHB-Lite adapters, initiators and targets.

  Language:Bluespec2602

• AWSteria_Infra

  "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)

  Language:VHDL14736

• brvf-tools

  A collection of tools used by various RISC-V projects

  Language:Python1600

• Flute

  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

  Language:Bluespec349221655

• mcu-core

  The source files comprising the MCU core

  Language:Bluespec0500

• mcu-release

  A release repository for the mcu class of CPUs

  Language:Bluespec2651

• Piccolo

  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

  Language:Verilog305242649

joestoy's Repositories