johan92

altera_opencl_sandbox

Bloom_pattern_search

Pattern search based on Bloom algorithm.

csr-map-generator

Generator for CSR mapping module

fpga-for-beginners

Repo with FPGA/Verilog/RTL examples. I use it in articles for demonstration.

fpga-hash-table

Simple hash table on Verilog (SystemVerilog)

fpga-risc-16

Making RISC-16 for academic purposes

fpga-shared-memory

Verilog (SystemVerilog) implementation of shared memory for multiport systems

fpga-sort-engine

Simple sort engine on Verilog.

verilog-coding-style

Verilog (SystemVerilog) coding style

yafpgatetris

Yet Another Tetris on FPGA Implementation

johan92/fpga-hash-table

Simple hash table on Verilog (SystemVerilog)

johan92/verilog-coding-style

Verilog (SystemVerilog) coding style

johan92/yafpgatetris

Yet Another Tetris on FPGA Implementation

johan92/csr-map-generator

Generator for CSR mapping module

johan92/altera_opencl_sandbox

johan92/fpga-risc-16

Making RISC-16 for academic purposes

johan92/fpga-shared-memory

Verilog (SystemVerilog) implementation of shared memory for multiport systems

johan92/fpga-sort-engine

Simple sort engine on Verilog.

johan92/Bloom_pattern_search

Pattern search based on Bloom algorithm.

johan92/fpga-for-beginners

Repo with FPGA/Verilog/RTL examples. I use it in articles for demonstration.

johan92/fpga-multiflow-pkt-gen

Try to implement multiflow packet generator with various rate settings

johan92/fpga-quadtree

johan92/johan92.github.io

My blog on github :)

johan92/s5_a10_ram_test

Simple project for M20K read/writing. It shows some problems in timing in Arria 10.