Notes for a Tutorial on Verilog that I have been posting on YouTube.
https://www.latticesemi.com/Products/FPGAandCPLD/iCE40
- IEEE 1364 Standards
- By Pong P. Chu
- FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version 1st Edition
- FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC Edition (The next edition of the above Verilog Examples book.)
- SystemVerilog Vs Verilog in RTL Design - Pong P. Chu (This looks like an intro/summary of the above SystemVerilog book.)
- Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
- https://en.wikipedia.org/wiki/Verilog
- Yosys
- Yosys Open SYnthesis Suite (This is the compiler I use in my tutorial.)
- Yosys Documentation including the YosysHQ Yosys Manual.
Many Universities tend to leave copies of IEEE standards laying around for the world to see. Find one for yourself: https://www.google.com/search?q=1364-2005+pdf
Peter Mathy's YouTube series on Verilog: https://www.youtube.com/user/mathys2000yt/videos He uses an older style module declaration (akin to the K&R vs ANSI C function definition styles.) I prefer the modern style where we need not type the names of the ports twice.