/sea_azpr

An AZPR SoC implementation on SEA FPGA Board.

Primary LanguageVerilogOtherNOASSERTION

Introduction

This project is an AZPR SoC implementation for SEA FPGA Board.

The AZPR SoC is a well-organized and easy-to-understand processor system-on-a-chip for educational purposes. The AZPR SoC is developed for the Japanese textbook 《CPU自作入門》 (Written by 水頭 一壽, 米澤 遼, and 藤田 裕士), which is then translated to Chinese book 《CPU自制入门》(Translated by Qian Zhao)。

Link

The original AZPR SoC files can be found here: https://gihyo.jp/book/2012/978-4-7741-5338-4/support

License

As requested by book authors, the source code of AZPR SoC is only for non-commercial usage. You are free to modify and redistribute, but you must mention original authors, they are Mr. 水頭 一壽, Mr. 米澤 遼 and Mr. 藤田 裕士.