Pinned Repositories
ci_arm_gcc_docker
arm-none-eabi-gcc compilation environment docker
ci_ecp5_docker
ci esp5 fpga of docker.
ci_git_deploy_docker
ci git deploy docker.
ci_hpm_docker
build hpm sdk chip program.
ci_ice40_docker
ice40 compilation environment docker.
ci_ipq40xx_docker
hiui
picorv32_ice40up5k_icesugar
Picorv32 example based on icesugar development board
riscv_fpga_doc
Open source riscv fpga documentation
SA5Z-BSP
SA5Z-BSP Development Framework
jorislee's Repositories
jorislee/ci_ecp5_docker
ci esp5 fpga of docker.
jorislee/hiui
jorislee/SA5Z-BSP
SA5Z-BSP Development Framework
jorislee/ci_arm_gcc_docker
arm-none-eabi-gcc compilation environment docker
jorislee/ci_hpm_docker
build hpm sdk chip program.
jorislee/ci_ice40_docker
ice40 compilation environment docker.
jorislee/ci_ipq40xx_docker
jorislee/ci_ipq60xx_docker
jorislee/ci_mt7621_docker
jorislee/ci_mt76x8_docker
jorislee/ci_ssd20x_docker
jorislee/ci_x86_64_docker
jorislee/lede
Lean's LEDE source
jorislee/litex
Build your hardware, easily!
jorislee/openwrt-ci
jorislee/openwrt-nginx-19.07
jorislee/oui
🐛 A framework used to develop Web interface for OpenWrt. Use Nginx + Vue3 + Lua.
jorislee/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
jorislee/PurPle-Pi-R1
SDK for IDO-SBC2D06, base on SSD20X V30 SDK.
jorislee/pythondata-cpu-vexriscv
Python module containing verilog files for vexriscv cpu (for use with LiteX).
jorislee/pythondata-cpu-vexriscv_smp
Python module containing verilog files for VexRiscv SMP CPU (for use with LiteX).
jorislee/Rosebud
Framework for FPGA-accelerated Middlebox Development
jorislee/run_java8_docker
jorislee/scto
jorislee/scto_optee
jorislee/sec_eth_lwip
lwip with simple IPsec and MACsec implementations
jorislee/ticydb
TicyDB is local key-value data-store library in single header written in C.
jorislee/verilog-ethernet
Verilog Ethernet components for FPGA implementation
jorislee/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
jorislee/VexRiscvBPluginGenerator