I am trying to do things with myhdl
fpga25_snip4.py and test_stroby.py are the files in myHDL test_random.v is the verilog generated file and in test_random_corrected.v i have made some changes that make it compile. I feel that after my changes I should re-simulate.
then there is a makefile and example-8k.pcf that declares the connection between signals and pins.